This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-278225, filed on Sep. 13, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a memory system which output a data signal and a data strobe signal in sync with a reference clock signal.
2. Related Background Art
Recently, processors and memories have been used for various electric apparatuses. With speeding-up of processors and development of IT (Information Technology), a high speed memory has been required. According to the requirement, a memory such as a DDR SDRAM which transfers data at two fold frequency in sync with an external clock has been developed.
In a conventional SDR SDRAM (Single Data Rate Synchronous DRAM), data has been transferred in sync with only rising edges of the clock. On the other hand, in DDR SDRAM (Double Data Rate Synchronous DRAM), data is transferred in sync with both of rising edges and falling edges of the clock. Because of this, the DDR SDRAM can obtain two fold of the transferring speed of the SDR SDRAM.
However, the higher the data transferring speed becomes, the narrower a valid period of data (data window) becomes, and it becomes difficult to acquire data at a receiver side. Because of this, DDR SDRAM is newly provided with a data strobe signal (DQS), and the data is acquired based on this DQS at the receiver side.
The DQS is a bi-directional signal in sync with the clock and used for both of data write and read. At the write time, the DQS and the write data DQ are received from an ASIC side to write them into the memory. Conversely, at the read time, the DQS is outputted from the memory, and the DQS and the DQ for the data read are received at the ASIC side.
Thus, because the DQS is synchronized with the DQ, it is necessary to equalize a wiring length (trace length) of the DQS with that of the DQ.
Here, the problem due to the high speeding-up is the timing for acquiring data at the read time. FIG. 7 is a diagram showing the timing for acquiring data at the write time and the read time, with regard to the bi-directional DQS prescribed by JEDEC-DDR.
As shown in FIG. 7, although the data acquisition at the write and read times are carried out at both edges of the rising and falling edges of the DQS, the problem occurs at the read time.
In the data acquisition at the write time, as shown in FIG. 7A, the clock edges of the DQS locate at the vicinity of center of the valid period of the write data signal DQ. Because of this, it is possible to surely acquire data at the rising edges of the DQS.
On the other hand, as shown in FIG. 7B, in the read time when data is acquired at the controller side, both edges of the DQS and the changing points of the DQ are substantially the same timing. Because of this, as shown in FIG. 8, timing and phase of the DQS are staggered by using the DLL circuit and the PLL circuit at the controller side, and the timing has to be adjusted so that both edges of the DQS are located at the vicinity of an intermediate point of the valid period of data.
However, as mentioned above, it is a burden for the controller side to provide the DLL circuit or the PLL circuit to the controller side. As a method of adjusting timing between the DQ and the DQS without providing the DLL circuit or the PLL circuit to the controller side, there is a method of adjusting wiring length between the memory and the controller. If the wiring length of the DQS is set to be longer than that of the DQ, the wiring delay time of the DQS becomes long in proportion to that of the DQ, and the DQS at the controller side can be set to the vicinity of the intermediate point of the valid period of data.
However, by the difference such as arrangement of patterns and the amount of load, the capacitance load of the DQS may become larger than that of the DQ. In this case, the rising and falling waveforms of data dull, and it becomes difficult to enlarge margin of the valid period of data.
FIG. 9 is a block diagram showing schematic configuration of a conventional memory system. The memory system of FIG. 9 has a controller 52 composing a memory 51 and an ASIC implemented on a print substrate. The memory 51 and the controller 52 sends and receives data via a transferring line 53 on the print substrate.
The memory 51 has a storage part 50 for inputting/outputting a data signal QR based on external address signals A1-An and inputting/outputting the data strobe signal QRS in sync with a data signal QR, an I/O buffer 54a for inputting/outputting the data signal DQ relating to the data signal QR, an I/O buffer 54b for inputting/outputting the data strobe signal DQS relating to the data strobe signal QRS, and an address latch circuit 50 for controlling driving ability of the I/O buffer 54a, 54b based on the external address signals A1 and A6.
Because the conventional address latch circuit shown in FIG. 9 does not separately adjust driver sizes of the I/O buffers 54a and 54b, it was impossible to perform fine adjustment of the DQ and the DQS in a simple method of extending trace length.
Furthermore, in the conventional address latch circuit, the driving ability of the I/O buffers 54a and 54b has been set to be equal to each other. Because of this, if the amount of load of the transferring path of the DQ is not equal to that of the DQS, the signal waveform on the transferring path with a large amount of the load may dull.
FIGS. 10A-10B are a signal waveform diagram of the DQ and the DQS. FIG. 10A is a signal waveform diagram in the case of not being influenced by noise, and FIG. 10B is a signal waveform diagram in the case of being influenced by noise. Solid lines of these diagrams show the case where the waveform dulls, and dotted lines thereof show the case where the waveform does not dull.
As evidenced by these diagrams, timing is staggered by with or without noise. If the waveform dulls, the signal changes gradually, and as a result, a timing when logic changes staggers. For example, in FIG. 10A, if the original time when logic of the signal changes is time xc3x970, the time staggers to time xc3x971 by dulling of the signal waveform. Similarly, when there is noise and the waveform also dulls, the time staggers to time xc3x972.
Thus, in the conventional memory system, the driving ability of the DQ and the DQS has not been separately controlled in the memory. Because of this, even if only the trace length is just extended, the waveform dulls by the change of the load, thereby complicating the timing adjustment. Accordingly, timing adjustment of the DQ and the DQS has to be performed by using the DLL circuit and the PLL circuit at the controller side, thereby complicating the inside configuration of the controller.
A semiconductor integrated circuit according to an embodiment of the present invention, comprising:
a first output driving part which outputs a data signal in sync with a reference clock signal;
a second output driving part which outputs a data strobe signal prescribing a timing of said data signal; and
a driving control part which separately controls driving ability of said first and second output driving parts.
Furthermore, a memory system according to an embodiment of the present invention, comprising:
a storage part which outputs a data signal corresponding to a designated address and a data strobe signal prescribing a timing of said data signal;
a first output driving part which outputs said data signal in sync with a reference clock signal;
a second output driving part which outputs said data strobe signal in sync with said data signal; and
a driving control part which separately controls driving ability of said first and second output driving parts.